Complexity levels of electronic device testing vary tremendously, from simple manual low-volume/low-complexity testing performed with perhaps an oscilloscope and voltmeter, to personal computer-based medium-scale testing, to large-scale/high-complexity automated test equipment (ATE). Manual and personal computer-based testing are typically applied when testing discrete devices, specific components of an integrated circuit, or portions of a printed circuit board. In contrast, ATE testing is used to test functionality of a plurality of complex integrated circuits (ICs) such as memory circuits or hundreds of dice on a wafer prior to sawing and packaging.
FIG. 1 shows a block diagram of an automated test system 100 of the prior art. The test system 100 includes a test system controller 101, a test head 105, and a test prober 107. The test system controller 101 is frequently a microprocessor-based computer and is electrically connected to the test head 105 by a communication cable 103. The test prober 107 includes a stage 109 on which a semiconductor wafer 111 may be mounted and a probe card 113 for testing devices under test (OUTS) on the semiconductor wafer 111. The stage 109 is movable to contact the wafer 111 with a plurality of test probes 115 on the probe card 113. The probe card 113 communicates with the test head 105 through a plurality of channel communications cables 117.
In operation, the test system controller 101 generates test data which are transmitted through the communication cable 103 to the test head 105. The test head in turn transmits the test data to the probe card 113 through the plurality of communications cables 117. The probe card then uses these data to probe DUTs (not shown explicitly) on the wafer 111 through the plurality of test probes 115. Test results are then provided from the DUTs on the wafer 111 back through the probe card 113 to the test head 105 for transmission back to the test system controller 101. Once testing is completed and known good dice are identified, the wafer 111 is diced.
Test data provided from the test system controller 101 are divided into individual test channels provided through the communications cable 103 and separated in the test head 105 so that each channel is carried to a separate one of the plurality of test probes 115. Channels from the test head 105 are linked by the channel communications cables 117 to the probe card 113. The probe card 113 then links each channel to a separate one of the plurality of test probes 115.
With reference to FIG. 2, a prior art tester portion 200 of a typical ATE system designed for high speed testing, such as memory applications, has a driver 201 and comparator 203 pair electrically connected through a transmission line 205 to a single pin on a device under test (DUT) 207. The driver 201 sends write signals to the DUT 207 through a resistive element 211 while the comparator 203 acts as a receiver for reading signals generated by the OUT 207. When the tester portion 200 is writing a signal to the DUT 207, the driver 201 is enabled by closing a write switch 209 and the comparator 203 is disabled by opening a read switch 213. During a read operation, the driver 201 is disabled by opening the write switch 209 and the comparator 203 is enabled by closing the read switch 213.
The physical length of the transmission line 205 is roughly four feet long in a typical ATE test cell used for wafer sort and three feet long in an ATE system used for package test. Since the transmission line 205 is so long, when the tester 200 is reading from the DUT 207, a 50 ohm parallel termination resistor 217 is added into the circuit by closing a termination switch 215. The 50 ohm termination resistor 217 is used to avoid reflections along the transmission line 205.
With reference to FIG. 3 and continued reference to FIG. 2, a typical 100 MHz waveform 300 produced by the prior art tester portion 200 is displayed. Closing the termination switch 215 during a read operation reduces an amplitude of the signal received by the comparator 203 to approximately 2.1 V compared with a 3.0 V output from the DUT 207. The amplitude is reduced since the 50 ohm termination resistor 217 creates a voltage divider. If the termination switch 215 is left open, the voltage divider effect is eliminated but reflections on the transmission line 205 produce a distorted waveform 400 (FIG. 4). For comparison, an actual waveform 500 (FIG. 5) emanating from the DUT 207 is shown in FIG. 5.
As is readily discernible by one skilled in the art with reference to the waveforms in FIGS. 3-5, to test the DUT 207 with a data rate of greater than 100 MHz during a read cycle, the termination switch 215 must be closed to prevent significant distortion of the read signal. The disadvantage of closing the termination switch 215 is that the DUT 207 must source enough current to drive the 50 ohm termination resistor 217. In today's handheld consumer electronics markets, customers demand several days of usage of their products (such as iPods® and other MP3 devices, cellular phones, digital cameras, etc.) before having to recharge batteries internal to the product. Consequently, more and more memory devices are being designed such that the output buffers conserve power (i.e., battery life). Hence, many memory devices increasingly cannot source the current to drive the 50 ohm termination resistor 217 required during ATE applications. Consequently, a maximum data rate for the testing the DUT 207 cannot be optimized.
For example, a typical memory device inside a contemporary cell phone runs at a frequency of 100 MHz. If the memory device cannot source enough current to drive the 50 ohm termination during ATE testing, the maximum test frequency will be only approximately 10 MHz. Furthermore, most memory devices are intended to be used in applications that do not require a 50 ohm termination since other devices are typically located in close proximity. When the memory device, or any other DUT, sources sufficient current to drive the 50 ohm termination during ATE testing, the electrical characteristics of the device change. Most notably; the 50 ohm termination creates a voltage divider and the DC levels measured at the comparator are attenuated.
One of the key reasons that the driver/receiver pair has been located physically far away from the DUT in prior art applications is due to the wide temperature range over which a DUT is tested. A common temperature test range is from −40° C. to +150° C. The prior art driver/receiver pair typically cannot operate over this large temperature range while maintaining performance specifications. The performance specifications are especially critical for parametric tests such as ICC and other leakage current tests.
Therefore, what is needed is a means to test a large plurality of DUTs in high speed applications while maintaining signal integrity read from the DUTs while ensuring that a full range of temperature testing can still occur.